ZpNetics’ Ronald Newman Unveils Super-Z Superscalar Processors
MARQUETTE, MICHIGAN, USA, July 18, 2022 /EINPresswire.com/ — After more than 40 years of R&D, Ronald Newman has succeeded in manufacturing his first set of Super-Z processors by deploying his Si and SiC manufacturing processes ” without light “.
Mr. Newman began R&D on processors coupled with R&D on operating systems, compilers, and EDAs in the early 1980s. Mr. Newman’s designs were first made with discrete components and in bit slices, then onto FPGA macroblocks and shared slices laid on a PCB. After 40 years of iterative development, Mr. Newman’s Super-Z and Super-V series processors use superscalar pipelines of six to thirty-two stages and two super-threads to thirty-two-super-threads (extensions to both are in R&D) to deliver unprecedented performance than any processor known to date by orders of magnitude. As is known, current designs execute instructions issued in order and are allowed to complete out of order, a standard approach of dual-issue superscalar COTS designs, as they provide reasonable performance with low silicon cost. Out-of-order completion prevents long-latency operations such as memory writes from blocking the pipeline if there are no data dependencies. Super-Z processors have extended this concept by adding SIMD/MIMD coupled “context” to the various pipelines, units and Super-V takes this a step further by redesigning with Super-VLIW instructions.
Since most execution units are duplicated, the Super-Z was designed to be able to issue a plethora of instruction combinations, so it is not limited to issuing the standard integer and floating point instructions. in parallel, etc. According to Newman and colleagues, the current “extinct” implementation of its Super-Z core can base the clock at 400 MHz (GHz+ speeds also achieved) and has achieved Coremarks above 2,000 and up to 5 300, depending on the Super-Z blocks deployed. Further extensions and optimizations are in progress to achieve better results.
Super-Z on-chip flash coupled with a host of on-chip peripherals such as a four-interrupt controller (INTC), six general-purpose timers (TMU), four real-time clocks (RTC), four serial interface channels ( eg, SCI, CAN), Dual User Cutoff Controller (UBC), and Programmable Power Management Controller are just a few of the many macro blocks implemented on the chip. The direct memory access controller (DMAC) has six channels. DMAC is excellent at moving blocks of memory around with almost no CPU intervention. This allows efficient transfers of data from main memory to graphics memory for example. Then there are I/O Units (IOU), Memory Management Units (MMU) and Page Units (PU) which at the basic level were designed with memory protection in mind. and security in mind, so that different threads of execution do not interfere with each other. other memory spaces and potentially cause operating system and application crashes.
The basic Super-Z core includes DSP and GPU macro blocks and excels in 3D calculations. Impressive 3D fixed/floating point hardware, where each of the four multipliers (f4muls) can receive two 32-bit values (80-bit and fixed also supported) and produce a multiplied result which is passed to a four-input adder. This hardware reads two 128-bit vectors (two sets of four 32-bit values) from register files, multiplies the four 32-bit pairs at the same time, adds the four products, and puts the 32-bit result back into the register file. This provides the equivalent of 288-bit data compression (2 x 128 + 32 = 288). It’s just a pipeline of 3D calculations. The same functionality is applied to DSP engines. Finally, the optional FPGA, PE-Array and MEM macro-blocks can be used in generic logic/mixed, parallel processing and/or mechanical/electrical implementations. Mr. Newman said: “The beauty of designing using macro blocks over 40+ years and limited resources, has allowed my designs to be truly versatile and malleable, allowing me to focus on R&D, not implementation. I continuously and iteratively apply this methodology to all my R&D and mathematics.
With the current push towards autonomy and security, the Super-Z incorporates several security-related features, including ECC memory support and the ability to run eight cores in synchronous mode with a full data trace for debugging. Additionally, Newman and his colleagues are working to complete documentation for various critical and security standards such as ISO 26262/IEC62443 and to extend LLVM (open source compiler) to support the Super-Z core architecture.
Mr. Newman said “finally I can replace all my FPGA/Macro/PCB hardware with these Super-Z and Super-V processors to further improve and expand the ‘light out’ concept and now focus largely on R&D in starting with three of my many holy grails: energy, recombinant DNA and synthetic intelligence.