TSMC details the advantages of its N3 node


Article By: Brian Santo

TSMC revealed how its next N3 node will compare to its current N5, and also talked about EDA support for the new node.

TSMC, which now accompanies its N5 process node, said its scalable N4 node will move to volume production this year. N3, which will provide more of a technology leap than N4, is expected to go into volume production in the second half of 2022. N3 will indeed offer customers the kind of performance improvements they might expect from a leap. major node, although the speed improvement will be in the low end of TSMC projected aspirations from last year; the company also narrowly missed its target of improving density.

The announcements were made at an event hosted by TSMC, the 2021 OIP Ecosystem Online Forum.

The foundry also highlighted the participation of its EDA partners in supporting the N3 node, to assure enthusiastic chip designers that the IC design and testing tools for N3 will be ready and available. Synopsys jumped in; he announced his tools to support N3 a full week before the TSMC event. Cadence then had its quarterly earnings call and mentioned its products supporting N3 only after being reprimanded by an analyst for not responding immediately to Synopsys. Siemens waited until the opening day of the TSMC conference to announce its N3 tools.

LC Lu, TSMC’s vice president for its design and technology platform, presented details of the company’s updated manufacturing capabilities. N4, the “easy migration path from N5”, will start volume production this year and provide a 6% decrease in die area. He is, as expected and announced, a modest shrink.

Lu began by offering some historical statistics on the move from N7 to N5, offering a perspective for future improvements from N5 to N3 (see table above, top right). The improvement in logical density in the last knot jump will be less than the improvement in density in the previous one – and less than expected. The speed improvement will also be less this time around, but at least the number was in the target range.

The benchmark for comparisons was an Arm A72 core. Lu said the numbers will certainly be different for different products, but the results obtained with the Arm core will be a good benchmark for other product designs.

TSMC has fine-tuned the processes at each node for specific end uses, especially high performance computing. HPC customers should request the N3 DTCO node variant. Lu said that by going from N5 to N3, customers will get 10% to 26% less power boost. Going from N5 to N3 DTCO would get a 22% increase, but only 16% less horsepower. In other words, designers can get extra speed at the expense of fuel efficiency.

Lu also provided some architectural details on how it works. The additional 12% of speed comes from

  • resize the cells (they are higher) which reduces the resistance of the source
  • a new cell structure specifically for HPC which includes faster rockers and an abutment via
  • and a new metal design: BEOL MiM (back end of line, metal-insulator-metal).
TSMC’s N3 DTCO node includes optimizations specifically for high performance computing or HPC. (Click on the image to enlarge.)

The performance improvements associated with switching from N5 (or higher) to N3 are not negligible. However, the amount of improvement offered by each successive node decreases – the integration of silicon cannot go further. This is why the industry is simultaneously exploring the exact opposite path, which in English would be “disintegration” – a word which, given the connotation, the industry may have wisely avoided in favor of “disintegration”.

… Disaggregation in the form of splitting functions that were previously separate, but then built into the chip, and now it’s better to redistribute them. There are some pretty significant challenges in splitting an SoC into multiple chips – or chiplets. Lu explained that partitioning the system requires decisions on

  • Packaging (the choices TSMC will make available include CoWoS, InFO_PoP, InFO_3D and SOIC),
  • Symmetric or asymmetric design partitioning, and
  • Balance system performance, horsepower, area, cost, and thermal hot spots.
Chiplet interface options, and the IP sources for each. (Click on the image to enlarge.)

The need for thermal analysis very early in the design is new for chiplets, Lu said. The old method of thermal analysis does not work with microchips, which is why TSMC worked with its EDA partners to find specific methods.

The juxtaposition of chipsets in different configurations can not only exacerbate existing thermal challenges, but can also lead to unique thermal problems; there is no way to get an overlap on a single die.

Performance testing is also a challenge because testing has always consisted of testing a single chip. Now the problem is how to access multiple chips and test them alone and together, especially given all the packaging and interconnect options. Lu said the IEEE 1149.1 / 1838 standard helps define how to access multichip architectures for testing.

TSMC is also placing more emphasis on RF. Lu reminded participants (well, the viewers – the event is virtual) that TSMC has been in high volume production at 28 nm for several years; this node is called N28. The next node will be called N16FFC. Normally, there is minimal benefit to be gained by reducing the size of RF circuits, but TSMC appears to be interested in meeting the needs of businesses with mixed signal designs. Lu pointed out that the DC power reduction of the N16FFC from the N28 node will be 25%, which Lu says will be “best for digital high-intensity millimeter wave applications.”

And, because RF expertise continues to be scarce, TSMC tries to make it easier for designers to create RF circuits. “In cooperation with our EDA partners, we offer a complete RF PDK and design workflows that can help streamline RF design,” Lu said. The company has 35 individual design tools (several from each major vendor) , as well as reference designs.

N3 by design

At the TSMC event, Siemens announced that its products certified for TSMC’s N3 and N4 processes include the Caliber nmPlatform platform, Siemens’ physical verification solution for IC approval, as well as the platform. Analog FastSPICE form, which provides circuit verification for analog nanometers, radio frequency (RF), mixed signals, memory, and custom digital circuits. Siemens also said it is also working closely with TSMC on advanced process certifications for Siemens’ Aprisa placement and routing solution.

Siemens has also partnered with TSMC to create a Design for Testability (DFT) flow for TSMC’s 3D silicon stacking architecture, based on vendor EDA’s Tessent software.

TSMC said it has 35 individual tools certified to support its smaller nodes. (Click on the image to enlarge.)

Last week, Synopsys announced that TSMC had certified its digital and custom design platforms for TSMC’s 3nm technology. According to the vendor, enhancements to the digital design flow it supports include faster sync close, full flow correlation from summary to location and route to sync, as well as physical approval. The platform has been enhanced to provide improved synthesis and global placement engines that optimize library cell selection and placement results. To support TSMC’s ultra-low voltage design closure, the Synopsys optimization engine has been enhanced to use new footprint optimization algorithms. These new technologies, which are the result of the strategic partnership between the companies, will help give the PPA a boost for designs on TSMC’s N3 process, the company said.

Unlike Siemens and Synopsys, Cadence has not made any official announcements in support of TSMC’s N3 announcement, but TSMC has made it clear that it is working with the three major EDA companies. Cadence’s only statement came during the question-and-answer session of the company’s recent earnings call.

Cadence CEO Anirudh Devgan said of TSMC: “We are working with them on a variety of things including 3D-IC integrity… one of the major mobile customers made a 3D-IC solution with that with us and TSMC. And one of the key things was the thermal profile and they used Celsius to validate silicon that Celsius is accurate for 3D-IC temperature simulation. So I think 3D-IC will grow. And that requires multiple products and multiple implementation streams and we’re pretty confident in our position. (The quote is from the appeal transcript compiled by The Motley Fool.)

This graph illustrates the performance improvements and power savings (or penalties) for each of TSMC’s smaller nodes. The Arm A78 is the benchmark. (Click on the image to enlarge.)

This article was originally published on EE time.

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