AMD Showcases More 3D Stacking Technologies at Hot Chips 33


Looking to the future: 3D chip stacking technology has yet to catch on, with only Intel Foveros reaching the Lakefield processor market and some Zen3 products with vertically stacked bezels are waiting behind the scenes. But at this year’s Hot Chips Symposium, AMD is already laying out where it intends to go from here, with ambitious ideas on how to apply the technology.

The 3D V-Cache AMD showcased at Computex is the (relatively) simple addition of an extra L3 cache to a Ryzen 9 5900X, resulting in a performance increase of around 15% in games. The 3D stacking arrangement allowed AMD to use a production process that allows denser SRAM for the upper die, fitting 64MB into space directly above the 32MB on the base die which had to be made of silicon suitable for both cache and computation.

All of this was done using silicon through vias (TSVs), connected to direct vertical copper-to-copper connections that are much closer to each other than “traditional” microbump technology.

AMD Claims 9 Micron Bump For Its Hybrid Direct Link Technology; by comparison, Intel Foveros was working on the order of 50 microns when it was implemented at Lakefield, the primary benchmark used for AMD’s claim of 3x efficiency gains and 15x higher density with its interconnections with respect to the obviously unspecified “other 3D architecture”.

Team Blue also offers a pitch of 36 microns for its upcoming Foveros Omni technology for use in Meteor Lake processors, and 10 microns in Foveros Direct, a hybrid solution that rivals more directly what AMD is showing here.

However, the two are not expected to arrive until 2023, while AMD has said their 3D stacked Ryzen chips will be mass-produced by the end of this year.

The company is also working with TSMC on more complex 3D stacking designs, with the ambition of stacking processor cores on top of each other, splitting up macroblocks of a processor (such as lower cache levels) between different layers, or even go down to the level of cutting circuits.

Stacking the computational silicon in particular presents unique challenges in supplying power to the upper arrays and removing heat from the lower arrays – one of the reasons AMD’s 3D V-Cache is only layered. on the base matrix cache, leaving the processor cores alone.

Of course, this all depends on how much improvement can be made in power, performance, area and cost (PPAC) metrics – and, of course, whether TSMC can continue to deliver its advanced packaging techniques into production. massive.

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